Security researchers from MIT claim to have devised a hardware solution to prevent cache timing attacks based on speculative execution, such as Spectre and Meltdown. Their approach, named Dynamically Allocated Way Guard (DAWG), splits the processor cache in variably-sized partitions to make it impossible for processes to snoop on other processes’ cache partitions.
Since their disclosure, various software defense mechanisms have been proposed for Spectre and Meltdown, but they are usually targeted to a specific variant of the attack and exact a toll on performance. Now, researchers from MIT Computer Science & Artificial Intelligence Laboratory (CSAIL) claim to have devised a mechanism that requires minimal hardware modifications to existing processor architectures to defend them against a broad class of side channel attacks with reasonable performance overhead.
Speculative execution, which Spectre and Meltdown exploit, is a mechanim that aims to improve the overall performance of a processor by allowing it to execute multiple instructions while waiting for memory, e.g., both branches of a conditional, then discard those that were not needed, e.g. those belonging to the non followed branch.
In a paper that will be presented in a few days at the annual IEEE/ACM International Symposium on Microarchitecture (MICRO) in Fukuoka City, Japan, researchers Kirianski, Lebedev and others demonstrate a secure partitioning scheme for set associative structures, including caches, that adds the notion of protection domains. Protection domains provide strong isolation between partitions of the set associative structure, and are able, according to the researchers’ claims, to detect and prevent cache hits, misses, and metadata updates.
(Image from MIT paper.)
The key idea at the core of DAWG is leveraging the usual design of conventional set-associative memories as the combination of a controller with a number of direct-mapped caches, called ways:
In order to implement Dynamically Allocated Way Guard (DAWG), we will allocate groups of ways to protection domains, restricting both cache hits and line replacements to the ways allocated to the protection domain from which the cache request was issued.
To implement such mechanism, DAWG requires some additional metadata to be associated with the cache, amounting to a 24-bit register for hardware thread. The register is used to store three 8-bit active domain selectors. In addition to this, each cache needs 256 bits to describe which ways are allowed for each active domain. The researchers also claim that DAWG requires little modification of current operating systems to take advantage of such mechanism.
Admittedlty, DAWG is not yet able to defend against all kinds of speculative attacks and its creators are at work to improve it and broaden its application scope. Furthermore, it is not clear yet whether Intel or other CPU manufacturers will adopt their approach but Kirianski and Lebedev are hopeful that will happen. InfoQ will keep reporting on this as well as other approaches and solutions to speculative execution-based attacks as they become available.
